The present invention relates generally to the field of integrated circuit layout, and more specifically to scan control testing of integrated circuits.
Scan chaining is a technique used in design for testing. The objective is to make testing easier by providing a simple way to set and observe every latch in an integrated circuit. The basic structure of scan includes an input signal and an output signal to define the input and output of the scan chain, a scan enable pin that, when asserted, prompts every latch in the design to be connected into a long shift register, and a clock signal used to control all of the latches in the chain. A scan chain requires a signal be passed through a scan control to enable all the latches to be monitored, which must be connected to the latches in the chain. These scan control elements are often added to a chip and incorporated into the existing connection structure.